Concern a disk with a sector size of 512 bytes, 2000 tracks per surface, 50 sectors per track, five double - sided platters, and average seek time of 10 milliseconds.              NTA NET JUNE 2020  Given below are two statements: Statement I: The disk has a total number of 2000 cylinders. Statement II: 51200 bytes is not a valid block size for the disk. In the light of the above statements, choose the correct answer from the options given below:

Concern a disk with a sector size of 512 bytes, 2000 tracks per surface, 50 sectors per track, five double - sided platters, and average seek time of 10 milliseconds.            NTA NET JUNE 2020  If T is the capacity of a track in bytes, and S is the capacity of each surface in bytes, then (T,S)= ______

Concern a disk with a sector size of 512 bytes, 2000 tracks per surface, 50 sectors per track, five double - sided platters, and average seek time of 10 milliseconds. NTA NET JUNE 2020 
What is the capacity of the disk in bytes?

Concern a disk with a sector size of 512 bytes, 2000 tracks per surface, 50 sectors per track, five double - sided platters, and average seek time of 10 milliseconds.                  NTA NET JUNE 2020 
If the disk platters rotate at 5400 rpm (Revolutions per minute), then approximately what is the maximum rotational delay?

Concern a disk with a sector size of 512 bytes, 2000 tracks per surface, 50 sectors per track, five double - sided platters, and average seek time of 10 milliseconds. NTA NET JUNE 2020 
If one track of data can be transferred per revolution, then what is the data transfer rate?

The Reduced Instruction Set Computer (RISC) characteristics are:                         NTA NET DECEMBER 2019 a. Single cycle instruction execution. b. Variable length instruction formats. c. Instructions that manipulates operands in memory. d. Efficient instruction pipeline. Choose the correct characteristics from the options given below:

A computer uses a memory unit of 512 K words of 32 bits each. A binary instruction code is stored in one word of the memory. The instruction has four parts: an addressing mode field to specify one of the two - addressing mode(direct and indirect), an operation code, a register code part to specify one of the 256 registers and an address part. How many bits are there in addressing mode part, an opcode part, register code part and the address part?                                   NTA NET DECEMBER 2019

A micro instruction format has microoperation field which is divided into 2 subfields F1 and F2, each of having 15 distinct microoperations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field AD. The address space is of 128 memory words. The size of the micro instruction is:                  NTA NET December 2019 

An instruction is stored at location 500 with its address field at location 501. The address field has the value 400. A processor register R1 contains the number 200. Match the addressing mode (List I) given below with effective address (List II) for the given instruction:                NTA NET DECEMBER 2019 

List - I	List - II (Effective Address)
A. Direct	(i) 200
B. Register Indirect	(ii) 902
C. Index with R1 as the index register	(iii) 400
D. Relative	(iv) 600

Match List - I with List - II:                      NTA NET DECEMBER 2019

List - I	List - II
A. Micro operation	(i) Specify micro operations
B. Micro programmed control Unit	(ii) Improve CPU Utilization
C. Interrupts	(iii) Control memory
D. Micro instruction	(iv) Elementary operation performed on data stored in registers

Choose the correct options from those given below:

Which of the following methods are used to pass any number of parameters to the operating system through system calls?                             NTA NET December 2019 

The Boolean expression AB+AB̅ + A̅C is unaffected by the value of the Boolean variable _______  ̅                                       NTA NET December 2019 

The following program is stored in the memory unit of the basic computer. Give the content of accumulator register in hexadecimal after the execution of the program.                        NTA NET December 2019 

Location	Instruction
010	CLA
011	ADD 016
012	BUN 014
013	HLT
014	AND 017
015	BUN 013
016	C1A5
017	93C6

Given following equation:                                                          NTA NET December 2019  (142)_b + (112)_b-2 = (75)₈, find base b.

A non - pipelined system takes 30ns to process a task. The same task can be processed in a four segment pipeline with a clock cycle of 10ns. Determine the speed up of the pipeline for 100 tasks.                                            NTA NET December 2019 

Match List I and List II:                                      NTA NET December 2019 

List - I	List - II
A. Isolated I/O	(i) same set of control signal for I/O and memory communication
B. Memory mapped I/O	(ii) Separate instructions for I/O and memory communication
C. I/O interface	(iii) requires controls signals to be transmitted between the communicating units.
D. Asynchronous data transfer	(iv) resolve the differences in central computer and peripherals

Choose the correct option from those given below:

Which of the following binary codes for decimal digits are self complementing?                        NTA NET December 2019  A. 8421 code B. 2421 code C. excess - 3 code D. excess - 3 gray code Choose the correct option:

CMOS is a Computer Chip on the motherboard, which is:                                 CBSE NET JULY 2018 

In RS flip - flop, the output of the flip - flop at time (t+1) is same as the output at time t, after the occurrence of a clock pulse if:                            CBSE NET JULY 2018 

Match the terms in List - I with the options given in List - II:                                                              CBSE NET JULY 2018   

List - I	List - II
A. Decoder	(i) 1 line to 2n lines
B. Multiplexer	(ii) n lines to 2n lines
C. De multiplexer	(iii) 2n lines to 1 line
	(iv) 2n lines to 2n-1 lines

The hexadecimal equivalent of the binary integer number 110101101 is:                                 CBSE NET JULY 2018 

Perform the following operation for the binary equivalent of the decimal numbers (-14)₁₀ + (-15)₁₀  CBSE NET JULY 2018  The solution in 8 - bit representation is:

Match the items in List - I and List - II                                                           CBSE NET JULY 2018 

List - I	List - II
A. Interrupts which can be delayed when a much highest priority interrupt has occurred	(i) Normal
B. Unplanned interrupts which occur while executing a program	(ii) Synchronous
C. Source of interrupts is in phase with the system clock	(iii) Maskable
	(iv) Exception

Which of the following mapping is not used for mapping process in cache memory?                                                        CBSE NET JULY 2018 

Simplify the following using K - map:                                    CBSE NET JULY 2018  F(A, B, C, D) = ∑ (0,1,2,8,9,12,13) d(A, B, C, D) = ∑ (10,11,14,15) d stands for don't care condition.

In 8085 microprocessor, What is the output of following program? CBSE NET JULY 2018 


LDA 8000H

MVI B, 30H

ADD B

STA 8001H

In computers subtraction is generally carried out by                                                    NTA NET December 2018 

Consider the following Boolean equations:                                                NTA NET December 2018 

(i) wx + w(x+y) + x(x+y)=x+wy

(ii) (wx̅(y+xz̅) + w̅x̅)y=x̅y

What can you say about the above equations?

Consider the following statements:                                                 NTA NET December 2018 

(i) Auto increment addressing mode is useful in creating self - relocating code.

(ii) If auto increment addressing mode is included in an instruction set architecture, then an additional ALU is required for effective address calculations.

(iii) In auto increment mode, the amount of increment depends on the size of the data item accessed.

Which of the above statements is / are true?

A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code and a register code part to specify one of 64 registers and an address part. How many bits are there in the operation code, the register code part and the address part?                                                                         NTA NET December 2018 

Consider the following x86 - assembly language instructions:                                                         NTA NET December 2018 

MOV AL, 153

NEG AL

The contents of the destination register AL(in 8-bit binary notation), the status of Carry Flag (CF) and Sign Flag(SF) after the execution of above instructions, are

Consider a disk pack with 32 surfaces, 64 tracks and 512 sectors per pack. 256 bytes of data are stored in a bit serial manner in a sector. The number of bits required to specify a particular sector in the disk is NTA NET December 2018 

Consider a system with 2 level cache. Access time of Level 1 cache, Level 2 cache and main memory are 0.5ns, 5 ns and 100ns respectively. The hit rates of Level 1 and Level 2 caches are 0.7 and 0.8, respectively. What is the average access time of the system ignoring the search time within the cache?                                 NTA NET December 2018